The invention relates to an analog of digital converter (ADC) for signals balanced about a datum level comprising a first ADC stage which comprises an input for receiving a first analog signal, means for generating one or more reference levels, a comparator for each reference level, each comparator operating to compare said first analog signal with its reference level, said first ADC stage also comprising a digital to analog converter for generating at its output a second analog signal which is an analog representation of the digital output of the first ADC stage; means for subtracting said second analog signal from the first analog signal to form a third analog signal; means for applying the third analog signal to the input of a further ADC stage, and means for combining the digital outputs of the ADC stages to form the digital output of the converter.
Such a converter is disclosed in U.S. Pat. No. 4099173 which describes a 2-step or half-flash ADC having two separate ADC stages, each having 7 reference levels and seven comparators.
Half-flash ADC's are part of a broader family or multi-stage flash converters. In operation, each ADC state generates a group of bits of the final output, from a group of the most significant bits (MSB) to the least significant group of bits (LSB), and subtracts the analog value of that group of bits from the input value to generate a residual signal which forms the input to the following stage.
A well know problem with ADC's is that d.c. offset signals may arise within comparators, in reference networks, in the input signal itself or otherwise. These offset errors reduce the accuracy of conversion and so some form of offset compensation is desirable. In subranging converters in particular the problem of offsets can become acute because with the formation of the residual signal, the offset errors can assume magnified proportions in the following stage.
Manual trimming of the ADC components is possible, but is not only laborious but also fails to compensate for offsets present in the input signal, or, more importantly, for changes which invariably occur due to ageing after trimming or in operation, as the result of temperature changes for example.
Automatic offset compensation in a half-flash ADC is known, for example from U.S. Pat. No. 4410876 wherein an accurate reference signal is periodically substituted for the real input signal and converted and stored as an error signal to be added in at the input over the next few samples. The above cited specification relates specifically to an ADC for video signals, and advantage is taken of the naturally occurring blanking periods to perform this calibration. In more general applications, however, the time taken for the extra conversion may be unacceptable.
In many applications, it is known that the signal to be converted is balanced about some fixed level, e.g. ground. In other words, the signal has a fixed mean value. Known examples of balanced signals include line codes for digital data transmission such as the Alternate Mark Inversion (AMI) and WAL2 codes.
U.S. Pat. No. 4380005 discloses an ADC which uses the constant mean level of a balanced input signal to perform a continuous offset compensation. A feedback signal is taken from the sign bit of the digital output, low pass filtered and subtracted from the input signal. However, the ADC disclosed in U.S. Pat. No. 4380005 is of a different type to that claimed in the present application and the problem of magnified offsets in the residual signal does not exist in the ADC disclosed.